The present invention relates to design and operation of high-frequency clocked digital circuit systems, and in particular to method and system for reducing delta I-noise in said digital circuit system.
The operation speed of today""s computer systems approach sub-nanosecond cycle times. The average switching activity and therefore the average power supply current I demand can fluctuate, i.e., change within few nanoseconds. E.g., delta-I=140A current fluctuation of the average power supply current is typical for the multiprocessor multi-chip module of the prior art IBM zSeries 900 system. The fluctuation of the average current demand can be periodic or non-periodic. Due to the parasitic inductance along the power distribution path from the power supply to the individual chips the on-chip power supply voltage deviates temporarily from its nominal level in reaction of a switching activity change. The expression xe2x80x9cfluctuationxe2x80x9d is used in here for denoting the rise or drop of a physical quantity, such as current I or supply voltage U, whereas the term xe2x80x9cchangexe2x80x9d will be primarily used for denoting a status transition associated with a given activity unit on the chip, e.g., from xe2x80x9cswitchingxe2x80x9d to xe2x80x9cquietxe2x80x9d. These power supply voltage deviations are called high- and mid-frequency delta-I noise.
In order to reduce the power supply delta-I noise, decoupling capacitors are placed in prior art along the power supply path, on chips, modules, cards and boards. These decoupling capacitors can sink and source extra current and thus reduce the impact of delta-I on the power supply voltage. However, the decoupling capacitors and all parasitic partial inductance of the power supply path also create resonance loops having various resonance frequencies, which may increase the delta-I noise, if a resonance frequency and the frequency of a periodic switching change coincide. This prior art is described in H. B. Bakoglu, xe2x80x9cCircuits, Interconnections, and Packaging for VLSIxe2x80x9d, Addison-Wesley Publishing Company, 1990, pp. 303-325, or in W. D. Becker, et al, xe2x80x9cModeling, Simulation and Measurement of Mid-Frequency Simultaneous Switching Noise in Computer Systemsxe2x80x9d, IEEE Trans. Compon., Packaging, and Manuf. Technol., Part B: Advanced Packaging, vol. 21, no. 2, pp. 157-163, May 1998, or in D. Herrell, B. Beker, xe2x80x9cPower system design for high performance PC microprocessorsxe2x80x9d, IEEE International Workshop on Chip-Package Codesign CPD""98, pp. 46-47, 1998.
Delta-I noise is one contribution to the overall power supply noise budget and can jeopardize system function and reliability.
FIG. 1 is intended to illustrate the general problem. It shows the on-chip power supply noise voltage after starting operation, i.e., switching with 1 nanosecond (ns) cycle time, and 140A average power supply current, which represents a delta-I current step from 0 A to 140 A. The power supply voltage behavior has been obtained by simulation and confirmed by measurements, see B. Garben, M. F. McAllister, xe2x80x9cNovel Methodology for Mid-Frequency Delta-I Noise Analysis of Complex Computer System Boards and Verification by Measurementsxe2x80x9d, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 69-72, 2000. High frequency noise (1 ns period) and mid frequency noise (132 ns period) are superimposed. The actual on-chip power supply voltage behaves the same around the nominal voltage level (e.g. 1.2V).
The damped mid-frequency oscillation with initially 57 mV peak on-chip power supply voltage noise is caused by the resonant loop consisting of all on-module capacitors, i.e., on-module power supply decoupling capacitors plus capacitance of all chips, all board decoupling capacitors and the effective power supply path loop inductance between the two sets of capacitors.
With reference to Plot a) of FIG. 2 the on-chip power supply noise voltage of the same packaging arrangement is shown, but now, switching and non-switching depicted as xe2x80x9cquietxe2x80x9d-time slots repeat every 66 ns. The delta-I repetition rate coincides with the package resonance of 132 ns. The peak on-chip power supply delta-I noise equals 74 mV during the 1st quiet time slot and increases to 103 mV during the 2nd quiet time slot. Both peak noise values exceed the 57 mV, seen during a single switching activity change. The peak mid-frequency on-chip power supply delta-I noise during periodic activity changes saturates at approx. 135 mV beyond 8 periods.
The saturated peak on-chip mid-frequency delta-I noise increases with increasing conductivity within the resonance loop. E.g. if the overall conductivity within the loop is doubled, the maximum on-chip noise reaches 202 mV after 10 periodic switching activity changes without any saturation tendency (FIG. 2, curve b). This example demonstrates how the peak on-chip power supply voltage noise of periodic/repeated activity changes can significantly exceed the peak values of a single activity change.
In prior art, high performance computer systems such as the IBM zSeries 900 apply the following technical features in order to damp the delta I-noise:
1. many decoupling capacitors on chips, on the Multi-Chip-Module (MCM) and on the board close to the MCM,
2. sandwiching of VDD and GND planes closely to each other, in cards and boards to provide a low effective power supply loop inductance.
However, these design efforts also reduce the effective resistance of the resonant loop and therefore increase the power supply delta-I noise sensitivity in case of a resonance condition.
Delta-I noise and its increase due to resonant effects is considered in the system noise budget and in signal timing calculations. The following two theoretical approaches are considered today to account for large non-periodic switching activity changes, whereas periodic activity changes are not regarded at all:
First, an increase of the chip operation voltage allowing shorter cycle times to avoid resonance. This, however, implies more power dissipation, which is not desired at all.
Second, stretching the system cycle time to avoid resonance. This however reduces the system performance, which also is not desired.
It is thus an objective of the present invention to provide a method and system for reducing delta I-noise in digital circuit systems.
According to the broadest aspect of the present invention a method and respective system is disclosed in a general approach for reducing delta-I noise in a digital circuit system comprised of a plurality of activity units being connected to a DC-supply voltage, in which method and system respectively, the operation of said digital circuit system may excite high-frequency fluctuations of a total supply current I (delta-I), and a respective resulting fluctuation of the supply voltage. Said method is characterized by the steps of:
a) maintaining a circuit system-specific catalogue storing the current consumption and delta-I for each of said activity units in its operational state,
b) continuously monitoring the actual current consumption of the total of said activity units,
c) determining critical operation conditions to be caused by an immediately imminent excess fluctuation of the supply voltage resulting from an immediately imminent delta-I demand, the excess quantity being defined relative to a predetermined set tolerance band for the total current I,
d) dependent of the quantity of the imminent delta-I demand selecting a subset of said activity units with a respective current delta-I demand, for either
aa) temporarily delaying their begin of activity in case of an imminent supply voltage drop, or
bb) temporarily continuing their activity with a predetermined, activity-specific No-Operation (NO-OP) phase in case of an imminent supply voltage rise.
During the physical system packaging design various power supply loop resonance frequencies (f_crit), the corresponding critical duty factor ranges (T=1/f_crit) and a maximum allowed single total delta-I demand (i_crit) value are determined by simulation and are coded into a system specific catalogue, i.e., xe2x80x9cdata base (SSDB)xe2x80x9d, then the critical excess voltage states, i.e., dropdowns, and rise peaks, can be supervised and avoided.
According to the present invention, throughout the system all major power consuming sub-units, i.e., said activity units, referred to herein as AU, mentioned above, which might be one chip or portion of a chip, or a group of activity units, contain a control element, referred to herein as CE, for monitoring and controlling the actual switching activity within the unit. The control element can force switching activity start delays and NO-OP (dummy) cycles on request within the AU. According to the invention all control elements and thus all sub-units are coordinated by a supervising unit, referred to herein as SU, in a way, which avoids overall periodic switching activity changes of the above mentioned plurality of critical resonance frequencies f_crit and keeps non-periodic switching activity changes and thus delta-I values below i_crit.
According to the invention there may be basically one supervising unit throughout the system to coordinate the change of total power consumption, or the system is split into several power domains having several supervising units. The SU decisions are based on the system specific data base. The SU can grant AUs having an actually active state to switch into a xe2x80x9cquietxe2x80x9d state and vice versa while keeping the overall system switching activity state change within particular predetermined bounds.
This basic controlling scheme is permanently used to control the delta-I power supply noise, in particular during system power-on, system test and during general system operation. This approach allows to operate systems, which would not be functional/reliable without this control.
The controlling scheme can also be used to guide the overall system activity to a mode where functional, delayed and NO-OP switching activities are interlaced or anti-cycled in a way, that the delta-I noise is actively damped. This is described in more detail below with reference to FIG. 5 curve b.
The above mentioned general approach thus basically needs:
a kind of supervisor unit performing steps a) to d) and communication between each AU and the supervisor unit which transfers the actual information ON/OFF for each activity unit. Thus, a damped delta-I-fluctuation behavior and thus a nearly constant supply voltage can be obtained over time.
Said general approach thus covers more than the more preferred particular request/grant approach which is a special case of the general approach. The delta in generality can be seen in the fact that the general approach includes solutions in which the AUs are treated as immediate command receivers, which must sometimes halt their operation even in cases in which this seems not adequate for sake of system performance.
The request grant approach assures that once an AU has begun operation it can continue operation until this is finished. Thus, a weaker intervention to the existing, finely balanced instruction handling in the chip circuit is done, which results in more performance compared to the general approach.
The basic method mentioned before, may be further improved, by further comprising a request/grant mechanism between a supervisor means and each of said activity units, whereby the mechanism comprises the steps of:
a) an activity unit requesting that its operation is required to begin (Go-request),
b) granting the request when this is compliant to the predetermined tolerance band, otherwise not granting said request,
c) on a successful grant, beginning operation of the AU,
d) an activity unit requesting that operation is required to stop (STOP-request),
e) granting the STOP-request when the respective stop of activity operation is compliant to the tolerance band, otherwise not granting said request,
f) on a successful grant, stopping the operation of the AU.
Here, the advantage is that the degree of intervention with the actual operational (functional) chip logic is quite small which results in robust control and improved circuit performance.
In other words, a method is described to reduce delta-I noise and guarantee safe digital system operation despite of critically periodic switching activity changes and/or large non-periodic switching activity changes of CMOS chips, e.g. microprocessors, storage arrangements.
The system operation jeopardizing critical conditions are identified by simulation during the physical system packaging design. According to the invention, during system operation the actual switching activity is continuously monitored. In case of a critical, imminent condition built-up, i.e., an excess fluctuation can be identified to be immediately expected, then additional non-switching or switching cycles are executed to de-escalate the critical condition. This approach allows to build and operate systems, which would not be functional and reliable without this control.
The following structural features are disclosed:
A digital circuit system comprised of a plurality of activity units being connected to a DC-supply voltage, the operation of which may excite high-frequency fluctuations of a total current I, and a respective resulting fluctuation of the supply voltage, is characterized by digital circuit means implemented for performing the steps of the method mentioned before.
In particular, the digital circuit system may be preferably characterized by the facts that
a) a subset of said activity units comprises a control element for issuing a STOP or GO request and for receiving a respective grant, whereby said grant triggers a begin and stop of operation of said activity units,
b) a supervisor control circuit is connected to said control elements via respective control signal lines or other communication means.
When the digital circuit system comprises a hard-wired request-grant wiring, then the advantage is that a very robust and high speed signaling scheme is obtained.
An activity unit may preferably be one of or a group of the following circuit functional elements:
a processor unit, an Arithmetic and Logical Unit (ALU), an adder stage, a multiplier stage, a bus multiplexer stage, a memory array, a switching stage, a clock tree, Input/Output (I/O) driver unit, or an analogue circuit component, in particular a current source. Of course, the composition of a group my be organized such that closely related working units are comprised of one group, which produce e.g., an intermediate result which is further input in a working unit associated with a different group.
An example for a group is an adder plus an adder output comparing stage.
Thus, an easy and robust calculating can be obtained when useful grouping of activity units is done.